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ivuorinen
2024-04-26 00:13:28 +00:00
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tldr/verilator
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@@ -5,7 +5,7 @@ source: https://github.com/tldr-pages/tldr.git
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# verilator
> Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
> Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
> More information: <https://veripool.org/guide/latest/>.
- Build a specific C project in the current directory: