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26 lines
836 B
Plaintext
26 lines
836 B
Plaintext
---
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syntax: markdown
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tags: [tldr, common]
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source: https://github.com/tldr-pages/tldr.git
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---
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# verilator
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> Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
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> More information: <https://veripool.org/guide/latest/>.
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- Build a specific C project in the current directory:
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`verilator --binary --build-jobs 0 -Wall {{path/to/source.v}}`
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- Create a C++ executable in a specific folder:
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`verilator --cc --exe --build --build-jobs 0 -Wall {{path/to/source.cpp}} {{path/to/output.v}}`
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- Perform linting over a code in the current directory:
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`verilator --lint-only -Wall`
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- Create XML output about the design (files, modules, instance hierarchy, logic, and data types) to feed into other tools:
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`verilator --xml-output -Wall {{path/to/output.xml}}`
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